Index: cpu/arm720t/interrupts.c =================================================================== --- a/cpu/arm720t/interrupts.c (.../vanilla/u-boot-1.1.1) (revision 160) +++ b/cpu/arm720t/interrupts.c (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -7,6 +7,9 @@ * Sysgo Real-Time Solutions, GmbH * Alex Zuepke * + * (C) Copyright 2004 + * Robert Schwebel, Pengutronix + * * See file CREDITS for list of people who contributed to this * project. * @@ -33,20 +36,40 @@ #ifdef CONFIG_NETARM #include #endif +#ifdef CONFIG_SOC_H7202 +#define CONFIG_ARCH_H720X y +#define CONFIG_CPU_H7202 y +#include +#endif extern void reset_cpu(ulong addr); -#ifndef CONFIG_NETARM -/* we always count down the max. */ -#define TIMER_LOAD_VAL 0xffff -/* macro to read the 16 bit timer */ -#define READ_TIMER (IO_TC1D & 0xffff) -#else +unsigned long foo; + +/* Macros to access timers */ + +#if defined (CONFIG_NETARM) +/* Net+ARM has a prescaler, use it */ #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE)) #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL)) #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS)) #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK +#define TIMER_INCREMENTS 0 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK) + +#elif defined (CONFIG_EP7312) +#define TIMER_LOAD_VAL 0xffff +#define TIMER_INCREMENTS 0 +#define READ_TIMER (IO_TC1D & 0xffff) + +#elif defined (CONFIG_SOC_H7202) +/* TODO: split into TIMER_PRELOAD_VALUE and TIMER_RANGE_VALUE */ +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_INCREMENTS 1 +#define READ_TIMER (CPU_REG(TIMER_PHYS,TM1_COUNT)) + +#else +#error "Please define timer macros!" #endif #ifdef CONFIG_USE_IRQ @@ -183,11 +206,11 @@ } static ulong timestamp; -static ulong lastdec; +static ulong latch; int interrupt_init (void) { -#ifdef CONFIG_NETARM +#if defined (CONFIG_NETARM) /* disable all interrupts */ IRQEN = 0; @@ -197,8 +220,10 @@ NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL)); /* set timer 2 counter */ - lastdec = TIMER_LOAD_VAL; -#else + latch = TIMER_LOAD_VAL; + +#elif defined (CONFIG_EP7312) + /* disable all interrupts */ IO_INTMR1 = 0; @@ -209,8 +234,29 @@ IO_SYSCON1 &= ~SYSCON1_TC1S; /* set timer 1 counter */ - lastdec = IO_TC1D = TIMER_LOAD_VAL; + latch = IO_TC1D = TIMER_LOAD_VAL; + +#elif defined (CONFIG_SOC_H7202) + + /* disable all interrupts */ + CPU_REG(IRQC_PHYS, IRQC_IER) = 0; + + /* period value */ + CPU_REG(TIMER_PHYS, TM1_PERIOD) = 0xFFFFFFFF; + + /* clean timer */ + CPU_REG(TIMER_PHYS, TM1_CTRL) |= 0x4; + CPU_REG(TIMER_PHYS, TM1_CTRL) &= ~0x4; + + /* start timer */ + CPU_REG(TIMER_PHYS, TM1_CTRL) |= 3; + + latch = READ_TIMER; + +#else +#error "Please implement interrupt_init for your board!" #endif + timestamp = 0; return (0); @@ -243,31 +289,26 @@ tmo *= CFG_HZ; tmo /= 1000; - tmo += get_timer (0); + reset_timer(); - while (get_timer_masked () < tmo) - /*NOP*/; + while ((get_timer_masked ()) < tmo); } void reset_timer_masked (void) { /* reset time */ - lastdec = READ_TIMER; + latch = READ_TIMER & 0xffff; timestamp = 0; } ulong get_timer_masked (void) { - ulong now = READ_TIMER; + ulong now = (READ_TIMER & 0xffff); - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; + /* this should work with up- and down counters! */ + timestamp += (((latch - now) * -1) + 0xffff) & 0xffff; + + latch = now; return timestamp; } Index: Makefile =================================================================== --- a/Makefile (.../vanilla/u-boot-1.1.1) (revision 160) +++ b/Makefile (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -57,7 +57,7 @@ CROSS_COMPILE = ppc_8xx- endif ifeq ($(ARCH),arm) -CROSS_COMPILE = arm-linux- +CROSS_COMPILE = arm-softfloat-linux-gnu- endif ifeq ($(ARCH),i386) ifeq ($(HOSTARCH),i386) @@ -1052,6 +1052,12 @@ ## ARM720T Systems ######################################################################### +h7202_config : unconfig + @./mkconfig $(@:_config=) arm arm720t h7202 + +kurzfu_config : unconfig + @./mkconfig $(@:_config=) arm arm720t h7202 + impa7_config : unconfig @./mkconfig $(@:_config=) arm arm720t impa7 Index: include/asm-arm/arch-arm720t/h720x-hardware.h =================================================================== --- a/include/asm-arm/arch-arm720t/h720x-hardware.h (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/include/asm-arm/arch-arm720t/h720x-hardware.h (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,328 @@ +/* + * linux/include/asm-arm/arch-h720x/hardware.h + * + * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc. + * (C) 2003 Thomas Gleixner + * (C) 2003 Robert Schwebel + * + * This file contains the hardware definitions of the h720x processors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Do not add implementations specific defines here. This files contains + * only defines of the onchip peripherals. Add those defines to boards.h, + * which is included by this file. + */ + +/* This file was taken from linux-2.4.21-rmk1-hynix14. */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#define IOCLK (3686400L) + +/* Onchip peripherals */ + +#define IO_VIRT 0xf0000000 /* IO peripherals */ +#define IO_PHYS 0x80000000 +#define IO_SIZE 0x00050000 + +/* Macro to access the CPU IO */ +#define CPU_IO(x) (*(volatile u32*)(x)) + +/* Macro to access general purpose regs (base, offset) */ +#define CPU_REG(x,y) CPU_IO(x+y) + +/* Macro to access irq related regs */ +#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x) + +/* CPU registers */ + +/* SDRAM controller */ +#define SD_PHYS 0x80000000 +#define SDCON_PHYS (SD_PHYS + 0x00) +#define SDREF_PHYS (SD_PHYS + 0x04) +#define SDWBF_PHYS (SD_PHYS + 0x08) +#define SDWAIT_PHYS (SD_PHYS + 0x0C) + +/* general purpose I/O */ +#define GPIO_VIRT (IO_VIRT + 0x23000) +#define GPIO_A_VIRT (GPIO_VIRT + 0X00) +#define GPIO_B_VIRT (GPIO_VIRT + 0x20) +#define GPIO_C_VIRT (GPIO_VIRT + 0x40) +#define GPIO_D_VIRT (GPIO_VIRT + 0x60) +#define GPIO_E_VIRT (GPIO_VIRT + 0x80) +#define GPIO_AMULSEL (GPIO_VIRT + 0xA4) + +/* Register offsets general purpose I/O */ +#define GPIO_DATA 0x00 +#define GPIO_DIR 0x04 +#define GPIO_MASK 0x08 +#define GPIO_STAT 0x0C +#define GPIO_EDGE 0x10 +#define GPIO_CLR 0x14 +#define GPIO_POL 0x18 +#define GPIO_EN 0x1C + +/*interrupt controller */ +#define IRQC_VIRT (IO_VIRT + 0x24000) +#define IRQC_PHYS (IO_PHYS + 0x24000) + +/* register offset interrupt controller */ +#define IRQC_IER 0x00 +#define IRQC_ISR 0x04 + +/* timer unit */ +#define TIMER_VIRT (IO_VIRT + 0x25000) +#define TIMER_PHYS (IO_PHYS + 0x25000) + +/* Register offsets timer unit */ +#define TM0_PERIOD 0x00 +#define TM0_COUNT 0x08 +#define TM0_CTRL 0x10 +#define TM1_PERIOD 0x20 +#define TM1_COUNT 0x28 +#define TM1_CTRL 0x30 +#define TM2_PERIOD 0x40 +#define TM2_COUNT 0x48 +#define TM2_CTRL 0x50 +#define TIMER_TOPCTRL 0x60 +#define TIMER_TOPSTAT 0x64 +#define T64_COUNTL 0x80 +#define T64_COUNTH 0x84 +#define T64_CTRL 0x88 +#define T64_BASEL 0x94 +#define T64_BASEH 0x98 + +/* Bitmaks timer unit TOPSTAT reg */ +#define TSTAT_T0INT 0x1 +#define TSTAT_T1INT 0x2 +#define TSTAT_T2INT 0x4 +#define TSTAT_T3INT 0x8 + +/* Bit description of TMx_CTRL register */ +#define TM_START 0x1 +#define TM_REPEAT 0x2 +#define TM_RESET 0x4 + +/* Bit description of TIMER_CTRL register */ +#define ENABLE_TM0_INTR 0x1 +#define ENABLE_TM1_INTR 0x2 +#define ENABLE_TM2_INTR 0x4 +#define TIMER_ENABLE_BIT 0x8 +#define ENABLE_TIMER64 0x10 +#define ENABLE_TIMER64_INT 0x20 + +/* PMU & PLL */ +#define PMU_BASE (IO_VIRT + 0x1000) +#define PMU_MODE 0x00 +#define PMU_STAT 0x20 +#define PMU_PLL_CTRL 0x28 + +/* PMU Mode bits */ +#define PMU_MODE_SLOW 0x00 +#define PMU_MODE_RUN 0x01 +#define PMU_MODE_IDLE 0x02 +#define PMU_MODE_SLEEP 0x03 +#define PMU_MODE_INIT 0x04 +#define PMU_MODE_DEEPSLEEP 0x07 +#define PMU_MODE_WAKEUP 0x08 + +/* Control bits for PMU/ PLL */ +#define PMU_WARMRESET 0x00010000 +#define PLL_CTRL_MASK23 0x000080ff + +/* LCD Controller */ +#define LCD_BASE (IO_VIRT + 0x10000) +#define LCD_CTRL 0x00 +#define LCD_STATUS 0x04 +#define LCD_STATUS_M 0x08 +#define LCD_INTERRUPT 0x0C +#define LCD_DBAR 0x10 +#define LCD_DCAR 0x14 +#define LCD_TIMING0 0x20 +#define LCD_TIMING1 0x24 +#define LCD_TIMING2 0x28 +#define LCD_TEST 0x40 + +/* 7201 */ +#define VGA_RAMBASE 0x50 +#define VGA_TIMING0 0x60 +#define VGA_TIMING1 0x64 +#define VGA_TIMING2 0x68 +#define VGA_TIMING3 0x6c + +/* LCD Control Bits */ +#define LCD_CTRL_LCD_ENABLE 0x00000001 + +/* Bits per pixel */ +#define LCD_CTRL_LCD_BPP_MASK 0x00000006 +#define LCD_CTRL_LCD_4BPP 0x00000000 +#define LCD_CTRL_LCD_8BPP 0x00000002 +#define LCD_CTRL_LCD_16BPP 0x00000004 +#define LCD_CTRL_LCD_BW 0x00000008 +#define LCD_CTRL_LCD_TFT 0x00000010 +#define LCD_CTRL_BGR 0x00001000 +#define LCD_CTRL_LCD_VCOMP 0x00080000 +#define LCD_CTRL_LCD_MONO8 0x00200000 +#define LCD_CTRL_LCD_PWR 0x00400000 +#define LCD_CTRL_LCD_BLE 0x00800000 +#define LCD_CTRL_LDBUSEN 0x01000000 + +/* VGA Control Bits (7201) */ +#define LCD_CTRL_VGA_ENABLE 0x00000100 +#define LCD_CTRL_VGA_BPP_MASK 0x00000600 +#define LCD_CTRL_VGA_4BPP 0x00000000 +#define LCD_CTRL_VGA_8BPP 0x00000200 +#define LCD_CTRL_VGA_16BPP 0x00000300 +#define LCD_CTRL_SHARE_DMA 0x00000800 +#define LCD_CTRL_VDE 0x00100000 +#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */ +#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */ + +/* Palette */ +#define LCD_PALETTE_BASE (IO_VIRT + 0x10400) +#define VGA_PALETTE_BASE (IO_VIRT + 0x10800) + +/* Serial ports */ +#define SERIAL0_VIRT (IO_VIRT + 0x20000) +#define SERIAL1_VIRT (IO_VIRT + 0x21000) + +#if defined (CONFIG_CPU_H7201) +#define SERIAL2_VIRT (IO_VIRT + 0x50100) +#define SERIAL3_VIRT (IO_VIRT + 0x50200) +#elif defined (CONFIG_CPU_H7202) +#define SERIAL2_VIRT (IO_VIRT + 0x2d000) +#define SERIAL3_VIRT (IO_VIRT + 0x2e000) +#else +#error processor definition mismatch +#endif + +#define SERIAL0_BASE SERIAL0_VIRT +#define SERIAL1_BASE SERIAL1_VIRT +#define SERIAL2_BASE SERIAL2_VIRT +#define SERIAL3_BASE SERIAL3_VIRT + +/* Matrix Keyboard Controller */ +#define KBD_VIRT (IO_VIRT + 0x22000) +#define KBD_KBCR 0x00 +#define KBD_KBSC 0x04 +#define KBD_KBTR 0x08 +#define KBD_KBVR0 0x0C +#define KBD_KBVR1 0x10 +#define KBD_KBSR 0x18 + +#define KBD_KBCR_SCANENABLE (1 << 7) +#define KBD_KBCR_NPOWERDOWN (1 << 2) +#define KBD_KBCR_CLKSEL_MASK (3) +#define KBD_KBCR_CLKSEL_PCLK2 0x0 +#define KBD_KBCR_CLKSEL_PCLK128 0x1 +#define KBD_KBCR_CLKSEL_PCLK256 0x2 +#define KBD_KBCR_CLKSEL_PCLK512 0x3 + +#define KBD_KBSR_INTR (1 << 0) +#define KBD_KBSR_WAKEUP (1 << 1) + +/* ADC converter */ +#define ADC_BASE (IO_VIRT + 0x29000) +#define ADC_CR 0x00 +#define ADC_TSCTRL 0x04 +#define ADC_BT_CTRL 0x08 +#define ADC_MC_CTRL 0x0C +#define ADC_STATUS 0x10 + +/* ADC control register bits */ +#define ADC_CR_PW_CTRL 0x80 +#define ADC_CR_DIRECTC 0x04 +#define ADC_CR_CONTIME_NO 0x00 +#define ADC_CR_CONTIME_2 0x04 +#define ADC_CR_CONTIME_4 0x08 +#define ADC_CR_CONTIME_ADE 0x0c +#define ADC_CR_LONGCALTIME 0x01 + +/* ADC touch panel register bits */ +#define ADC_TSCTRL_ENABLE 0x80 +#define ADC_TSCTRL_INTR 0x40 +#define ADC_TSCTRL_SWBYPSS 0x20 +#define ADC_TSCTRL_SWINVT 0x10 +#define ADC_TSCTRL_S400 0x03 +#define ADC_TSCTRL_S200 0x02 +#define ADC_TSCTRL_S100 0x01 +#define ADC_TSCTRL_S50 0x00 + +/* ADC Interrupt Status Register bits */ +#define ADC_STATUS_TS_BIT 0x80 +#define ADC_STATUS_MBT_BIT 0x40 +#define ADC_STATUS_BBT_BIT 0x20 +#define ADC_STATUS_MIC_BIT 0x10 + +/* Touch data registers */ +#define ADC_TS_X0X1 0x30 +#define ADC_TS_X2X3 0x34 +#define ADC_TS_Y0Y1 0x38 +#define ADC_TS_Y2Y3 0x3c +#define ADC_TS_X4X5 0x40 +#define ADC_TS_X6X7 0x44 +#define ADC_TS_Y4Y5 0x48 +#define ADC_TS_Y6Y7 0x50 + +/* battery data */ +#define ADC_MB_DATA 0x54 +#define ADC_BB_DATA 0x58 + +/* Sound data register */ +#define ADC_SD_DAT0 0x60 +#define ADC_SD_DAT1 0x64 +#define ADC_SD_DAT2 0x68 +#define ADC_SD_DAT3 0x6c +#define ADC_SD_DAT4 0x70 +#define ADC_SD_DAT5 0x74 +#define ADC_SD_DAT6 0x78 +#define ADC_SD_DAT7 0x7c + +/* + * PCMCIA + */ +#if defined (CONFIG_ARCH_H7201) +#define PCMCIA0_ATT_BASE 0xe5000000 +#define PCMCIA0_ATT_SIZE 0x00200000 +#define PCMCIA0_ATT_START 0x20000000 +#define PCMCIA0_MEM_BASE 0xe5200000 +#define PCMCIA0_MEM_SIZE 0x00200000 +#define PCMCIA0_MEM_START 0x24000000 +#define PCMCIA0_IO_BASE 0xe5400000 +#define PCMCIA0_IO_SIZE 0x00200000 +#define PCMCIA0_IO_START 0x28000000 + +#define PCMCIA1_ATT_BASE 0xe5600000 +#define PCMCIA1_ATT_SIZE 0x00200000 +#define PCMCIA1_ATT_START 0x30000000 +#define PCMCIA1_MEM_BASE 0xe5800000 +#define PCMCIA1_MEM_SIZE 0x00200000 +#define PCMCIA1_MEM_START 0x34000000 +#define PCMCIA1_IO_BASE 0xe5a00000 +#define PCMCIA1_IO_SIZE 0x00200000 +#define PCMCIA1_IO_START 0x38000000 + +#define PRIME3C_BASE 0xf0050000 +#define PRIME3C_SIZE 0x00001000 +#define PRIME3C_START 0x10000000 +#endif + +/* General defines to pacify gcc */ +#define PCIO_BASE (0) /* for inb, outb and friends */ +#define PCIO_VIRT PCIO_BASE + +/* + * DMA (MEMC) compatability + */ +#define HALF_SAM vram_half_sam +#define VDMA_ALIGNMENT (HALF_SAM * 2) +#define VDMA_XFERSIZE (HALF_SAM) +#define VDMA_INIT IOMD_VIDINIT +#define VDMA_START IOMD_VIDSTART +#define VDMA_END IOMD_VIDEND + +#endif /* __ASM_ARCH_HARDWARE_H */ Index: include/version.h =================================================================== --- a/include/version.h (.../vanilla/u-boot-1.1.1) (revision 160) +++ b/include/version.h (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 1.1.1" +#define U_BOOT_VERSION "U-Boot 1.1.1-hynix2-svn" #endif /* __VERSION_H__ */ Index: include/configs/kurzfu.h =================================================================== --- a/include/configs/kurzfu.h (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/include/configs/kurzfu.h (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2004 Robert Schwebel, Pengutronix + * + * Configuation settings for the Hynix H7202 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start U-Boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_SOC_H7202 1 /* in a Hynix H7202 SoC */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x08000300 +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CFG_NS16550 1 +#define CFG_NS16550_SERIAL 1 /* Integrated 16C550 UART */ +#define CFG_NS16550_REG_SIZE -4 /* 4 bytes register length, padded */ +#define CONFIG_CONS_INDEX 1 /* use serial line 1 */ +#define CFG_NS16550_COM1 0x80020000 +#define CFG_NS16550_CLK 3686400 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_JFFS2|CFG_CMD_DHCP|CFG_CMD_AUTOSCRIPT) & ~CFG_CMD_NFS) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs ip=dhcp" +/*#define CONFIG_NETMASK 255.255.0.0 */ +/*#define CONFIG_IPADDR 172.22.2.128 */ +/*#define CONFIG_SERVERIP 172.22.2.126 */ +/*#define CONFIG_BOOTFILE "impa7" */ +#define CONFIG_BOOTCOMMAND "dhcp;bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "kurzfu> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x40400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x40800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x40500000 /* default load address */ + +#define CFG_HZ 3686400 /* decrementer freq: 3.6864 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM FIXME */ +#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE 0 /* Flash starts at 0x0 */ + +#define CONFIG_ARCH_NUMBER 318 +#define FLASH_BUS_WIDTH 2 /* 16bit */ +#define FLASH_INTERLEAVE 1 /* made of one chip */ +#define FLASH_SECT_SIZE (128*1024) +#define FLASH_BANK_SIZE (1024*1024*16) +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (FLASH_SECT_SIZE) +#define CFG_ENV_SIZE (FLASH_SECT_SIZE) + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 2 +#define CFG_JFFS2_NUM_BANKS 1 + +#endif /* __CONFIG_H */ Index: include/configs/h7202.h =================================================================== --- a/include/configs/h7202.h (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/include/configs/h7202.h (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2004 Robert Schwebel, Pengutronix + * + * Configuation settings for the Hynix H7202 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start U-Boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#define CONFIG_INIT_CRITICAL + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_SOC_H7202 1 /* in a Hynix H7202 SoC */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */ + +/* + * Hardware drivers + */ +#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ +#define CS8900_BASE 0x08000300 +#define CS8900_BUS16 1 +#undef CS8900_BUS32 + +/* + * select serial console configuration + */ +#define CFG_NS16550 1 +#define CFG_NS16550_SERIAL 1 /* Integrated 16C550 UART */ +#define CFG_NS16550_REG_SIZE -4 /* 4 bytes register length, padded */ +#define CONFIG_CONS_INDEX 1 /* use serial line 1 */ +#define CFG_NS16550_COM1 0x80020000 +#define CFG_NS16550_CLK 3686400 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_JFFS2|CFG_CMD_DHCP) & ~CFG_CMD_NFS) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ETHADDR 08:00:3e:21:c7:f7 +#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs ip=dhcp" +/*#define CONFIG_NETMASK 255.255.0.0 */ +/*#define CONFIG_IPADDR 172.22.2.128 */ +/*#define CONFIG_SERVERIP 172.22.2.126 */ +/*#define CONFIG_BOOTFILE "impa7" */ +#define CONFIG_BOOTCOMMAND "dhcp;bootm" + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x40400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x40800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x40500000 /* default load address */ + +#define CFG_HZ 3686400 /* decrementer freq: 3.6864 MHz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM FIXME */ +#define PHYS_SDRAM_1 0x40000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE 0 /* Flash starts at 0x0 */ + +#define CONFIG_ARCH_NUMBER 162 +#define FLASH_BUS_WIDTH 4 /* 32bit */ +#define FLASH_INTERLEAVE 2 /* made of two 16bit chips */ +#define FLASH_SECT_SIZE (256*1024) +#define FLASH_BANK_SIZE (1024*1024*64) +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (FLASH_SECT_SIZE) +#define CFG_ENV_SIZE (FLASH_SECT_SIZE) + +/* Flash banks JFFS2 should use */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_FIRST_SECTOR 2 +#define CFG_JFFS2_NUM_BANKS 1 + +#endif /* __CONFIG_H */ Index: board/h7202/memsetup.S =================================================================== --- a/board/h7202/memsetup.S (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/memsetup.S (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,192 @@ +/* + * Memory Setup, inspired by Hynix Armon bootloader sequence + * + * (C) Copyright 2004 Robert Schwebel, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* PMUMODE */ +PMUMODE: .long 0x80001000 +PMUCLK: .long 0x80001028 + +/* H720x SDRAM Controller */ +SDCON: .long 0x80000000 +SDREF: .long 0x80000004 +SDWBF: .long 0x80000008 +SDWAIT: .long 0x8000000C + +/* move to hardware.h */ +#define SDCON_S1 (1<<31) +#define SDCON_S0 (1<<30) +#define SDCON_W (1<<24) +#define SDCON_R (1<<23) +#define SDCON_A (1<<22) +#define SDCON_C1 (1<<21) +#define SDCON_C0 (1<<20) +#define SDCON_D (1<<19) +#define SDCON_C (1<<18) +#define SDCON_B (1<<17) +#define SDCON_E1 (1<<7) +#define SDCON_B1 (1<<6) +#define SDCON_E0 (1<<3) +#define SDCON_B0 (1<<2) + +#define CFG_SDCON 0x00e200cc +#define CFG_SDWBF 0x00000000 +#define CFG_SDREF 0x190 + +.globl memsetup +memsetup: + + mov r6, lr /* push... */ + + /* Configure CPU frequency ---------------------------------------- */ + /* */ + /* 0x76: 100.00 MHz 0x6a: 77.41 MHz 0x62: 62.66 MHz */ + /* 0x73: 94.00 MHz 0x69: 75.57 MHz 0x61: 60.82 MHz */ + /* 0x72: 92.16 MHz 0x68: 73.72 MHz 0x60: 58.98 MHz */ + /* 0x6f: 86.63 MHz 0x67: 71.88 MHz 0x5f: 57.13 MHz */ + /* 0x6e: 84.78 MHz 0x66: 70.04 MHz 0x5e: 55.29 MHz */ + /* 0x6d: 82.94 MHz 0x65: 68.19 MHz 0x5d: 53.45 MHz */ + /* 0x6c: 81.10 MHz 0x64: 66.35 MHz 0x5c: 51.60 MHz */ + /* 0x6b: 79.25 MHz 0x63: 64.51 MHz 0x5b: 49.76 MHz */ + + ldr r0, PMUCLK + ldr r1, [r0, #0x0] + bic r1, r1, #0xff /* clean */ + orr r1, r1, #0x66 /* 70.04 MHz */ + str r1, [r0, #0x0] + + /* Initialize PMUMODE --------------------------------------------- */ + ldr r0, PMUMODE + mov r1, #0x1 + str r1, [r0, #0x0] + + /* Initialize SDRAM controller ------------------------------------ */ + + /* - set B=1: write buffer enable */ + /* - set [C1:C0]=10: CAS latency 2 */ + /* - set E0=0, E1=0, R=0: Idle Mode */ + + ldr r0, SDCON + mov r1, #0x0 + orr r1, r1, #(SDCON_C1|SDCON_B) + str r1, [r0, #0x0] + + bl delay4096us + + /* set E1=1, R=0: precharge device */ + + orr r1, r1, #(SDCON_E1) + str r1, [r0, #0x0] + + bl delay4096us + + /* Set Controller Refresh Timer Register to 0x10 */ + + ldr r2, SDREF + mov r1, #0x10 + str r1, [r2, #0] + + bl delay4096us + + /* auto refresh: R=1, E[1:0]=00 */ + mov r1, #0x0 + orr r1, r1, #(SDCON_C1|SDCON_B|SDCON_R) + str r1, [r0, #0x0] + + bl delay4096us + + /* SDRAM Mode Register Setting */ + + mov r1, #(0x20<<11) + add r1, r1, #0x01800 + add r1, r1, #0x44000000 + ldr r1, [r1, #0] + mov r0, r1 + + mov r1, #(0x20<<11) + add r1, r1, #0x01800 + add r1, r1, #0x46000000 + ldr r1, [r1, #0] + mov r0, r1 + + /* Write configuration value to SDCON */ + + ldr r0, SDCON + ldr r2, =CFG_SDCON + str r2, [r0, #0] + + /* Write configuration value to SDWBF */ + ldr r0, SDWBF + ldr r2, =CFG_SDWBF + str r2, [r0, #0] + + /* Write configuration value to SDREF */ + ldr r0, SDREF + ldr r2, =CFG_SDREF + str r2, [r0, #0] + + ldr r0, =0x80023000 + mov r2, #7 + str r2, [r0] + + /* Initialize CS2: Ethernet Controller ---------------------------- */ + + ldr r0, =0x80003008 + mov r2, #1 + str r2, [r0] + + mov lr, r6 /* ... pop */ + + mov pc, lr /* return */ + + +/* ------------------------------------------------------------------------ */ +/* delay4096us: */ +/* */ +/* modifies: r5, r4, r3 */ +/* ------------------------------------------------------------------------ */ + +delay4096us: + mov r5, lr /* push lr */ + + mov r4, #0x1000 +_delay4096us: + bl delay10us + sub r4, r4, #1 + cmp r4, #0 + bne _delay4096us + + mov lr, r5 /* pop lr */ + mov pc, lr + +delay10us: + mov r3, #10 +_delay1us: + sub r3, r3, #1 + cmp r3, #0 + bne _delay1us + mov pc, lr + +/* ------------------------------------------------------------------------ */ Index: board/h7202/intel.h =================================================================== --- a/board/h7202/intel.h (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/intel.h (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2002 ETC s.r.o. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the ETC s.r.o. nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Written by Marcel Telka , 2002. + * + * Documentation: + * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, + * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 + * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, + * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 + * + * This file is taken from OpenWinCE project hosted by SourceForge.net + * + */ + +#ifndef FLASH_INTEL_H +#define FLASH_INTEL_H + +#include + +/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ + +#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ +#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ + +/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ + +#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ +#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ + +/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ + +#define CFI_CHIP_INTEL_28F320J3A 0x0016 +#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" +#define CFI_CHIP_INTEL_28F640J3A 0x0017 +#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" +#define CFI_CHIP_INTEL_28F128J3A 0x0018 +#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" + +/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ + +#define CFI_CHIP_INTEL_28F640K3 0x8801 +#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" +#define CFI_CHIP_INTEL_28F128K3 0x8802 +#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" +#define CFI_CHIP_INTEL_28F256K3 0x8803 +#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" +#define CFI_CHIP_INTEL_28F640K18 0x8805 +#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" +#define CFI_CHIP_INTEL_28F128K18 0x8806 +#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" +#define CFI_CHIP_INTEL_28F256K18 0x8807 +#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" + +#endif /* FLASH_INTEL_H */ Index: board/h7202/h7202.c =================================================================== --- a/board/h7202/h7202.c (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/h7202.c (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2004 + * Robert Schwebel, Pengutronix + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#define CONFIG_ARCH_H7202 y +#define CONFIG_CPU_H7202 y +#include + +/* ------------------------------------------------------------------------- */ + +/* + * Miscelaneous platform dependent initialisations + */ + +int +board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_arch_number = CONFIG_ARCH_NUMBER; + gd->bd->bi_boot_params = 0x40000100; + gd->bd->bi_baudrate = CONFIG_BAUDRATE; + + /* enable UARTs */ + CPU_REG(0x80020000, 0x30) = 0x1; + + return 0; +} + +int +dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} Index: board/h7202/u-boot.lds =================================================================== --- a/board/h7202/u-boot.lds (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/u-boot.lds (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm720t/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} Index: board/h7202/config.mk =================================================================== --- a/board/h7202/config.mk (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/config.mk (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,24 @@ +# +# (C) Copyright 2004 +# Robert Schwebel, Pengutronix +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x41fe0000 Index: board/h7202/Makefile =================================================================== --- a/board/h7202/Makefile (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/Makefile (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,47 @@ +# +# (C) Copyright 2004 +# Robert Schwebel, Pengutronix +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := h7202.o flash.o +SOBJS := memsetup.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### Index: board/h7202/flash.c =================================================================== --- a/board/h7202/flash.c (.../vanilla/u-boot-1.1.1) (revision 0) +++ b/board/h7202/flash.c (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -0,0 +1,309 @@ +/* + * Copyright (C) 2003 ETC s.r.o. + * + * This code was inspired by Marius Groeger and Kyle Harris code + * available in other board ports for U-Boot + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Written by Peter Figuli , 2003. + * + */ + +#include +#include "intel.h" + + +/* + * This code should handle CFI FLASH memory device. This code is very + * minimalistic approach without many essential error handling code as well. + * Because U-Boot actually is missing smart handling of FLASH device, + * we just set flash_id to anything else to FLASH_UNKNOW, so common code + * can call us without any restrictions. + * TODO: Add CFI Query, to be able to determine FLASH device. + * TODO: Add error handling code + * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but + * hopefully may work with other configurations. + */ + +#if ( FLASH_BUS_WIDTH == 1 ) +# define FLASH_BUS vu_char +# if ( FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# else +# error "With 8bit bus only one chip is allowed" +# endif + + +#elif ( FLASH_BUS_WIDTH == 2 ) +# define FLASH_BUS vu_short +# if ( FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 8 )| x ) +# else +# error "With 16bit bus only 1 or 2 chip(s) are allowed" +# endif + + +#elif ( FLASH_BUS_WIDTH == 4 ) +# define FLASH_BUS vu_long +# if ( FLASH_INTERLEAVE == 1 ) +# define FLASH_CMD( x ) x +# elif ( FLASH_INTERLEAVE == 2 ) +# define FLASH_CMD( x ) (( x << 16 )| x ) +# elif ( FLASH_INTERLEAVE == 4 ) +# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x ) +# else +# error "With 32bit bus only 1,2 or 4 chip(s) are allowed" +# endif + +#else +# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration" +#endif + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +static FLASH_BUS flash_status_reg (void) +{ + + FLASH_BUS *addr = (FLASH_BUS *) 0; + + *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER); + + return *addr; +} + +static int flash_ready (ulong timeout) +{ + int ok = 1; + + reset_timer_masked (); + while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) != + FLASH_CMD (CFI_INTEL_SR_READY)) { + if (get_timer_masked () > timeout && timeout != 0) { + ok = 0; + break; + } + } + return ok; +} + +ulong flash_init (void) +{ + int i; + unsigned long address = CFG_FLASH_BASE; + + flash_info[0].size = FLASH_BANK_SIZE; + flash_info[0].sector_count = CFG_MAX_FLASH_SECT; + flash_info[0].flash_id = INTEL_MANUFACT; + memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT); + + for (i = 0; i < CFG_MAX_FLASH_SECT; i++) { + flash_info[0].start[i] = address; + address += FLASH_SECT_SIZE; + } + + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + return FLASH_BANK_SIZE; +} + +void flash_print_info (flash_info_t * info) +{ + int i; + + printf (" Intel vendor\n"); + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if (!(i % 5)) { + printf ("\n"); + } + + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, non_protected = 0, sector; + int rc = ERR_OK; + + FLASH_BUS *address; + + for (sector = s_first; sector <= s_last; sector++) { + if (!info->protect[sector]) { + non_protected++; + } + } + + if (!non_protected) { + return ERR_PROTECTED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + flag = disable_interrupts (); + + + /* Start erase on unprotected sectors */ + for (sector = s_first; sector <= s_last && !ctrlc (); sector++) { + if (info->protect[sector]) { + printf ("Protected sector %2d skipping...\n", sector); + continue; + } else { + printf ("Erasing sector %2d ... ", sector); + } + + address = (FLASH_BUS *) (info->start[sector]); + + *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE); + *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM); + if (flash_ready (CFG_FLASH_ERASE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + printf ("ok.\n"); + } else { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + break; + } + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + } + if (ctrlc ()) + printf ("User Interrupt!\n"); + + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data) +{ + FLASH_BUS *address = (FLASH_BUS *) dest; + int rc = ERR_OK; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*address & data) != data) { + return ERR_NOT_ERASED; + } + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + + flag = disable_interrupts (); + + *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER); + *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1); + *address = data; + + if (!flash_ready (CFG_FLASH_WRITE_TOUT)) { + *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND); + rc = ERR_TIMOUT; + printf ("timeout! Aborting...\n"); + } + + *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY); + if (flag) { + enable_interrupts (); + } + + return rc; +} + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong read_addr, write_addr; + FLASH_BUS data; + int i, result = ERR_OK; + + + read_addr = addr & ~(sizeof (FLASH_BUS) - 1); + write_addr = read_addr; + if (read_addr != addr) { + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (read_addr < addr || cnt == 0) { + data |= *((uchar *) read_addr) << i * 8; + } else { + data |= (*src++) << i * 8; + cnt--; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + } + for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) { + if ((result = write_data (info, write_addr, + *((FLASH_BUS *) src))) != ERR_OK) { + return result; + } + write_addr += sizeof (FLASH_BUS); + src += sizeof (FLASH_BUS); + } + if (cnt > 0) { + read_addr = write_addr; + data = 0; + for (i = 0; i < sizeof (FLASH_BUS); i++) { + if (cnt > 0) { + data |= (*src++) << i * 8; + cnt--; + } else { + data |= *((uchar *) read_addr) << i * 8; + } + read_addr++; + } + if ((result = write_data (info, write_addr, data)) != 0) { + return result; + } + } + return ERR_OK; +} Index: drivers/ns16550.c =================================================================== --- a/drivers/ns16550.c (.../vanilla/u-boot-1.1.1) (revision 160) +++ b/drivers/ns16550.c (.../u-boot-hynix/releases/u-boot-1.1.1-hynix3) (revision 160) @@ -12,7 +12,8 @@ #define LCRVAL LCR_8N1 /* 8 data, 1 stop, no parity */ #define MCRVAL (MCR_DTR | MCR_RTS) /* RTS/DTR */ -#define FCRVAL (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR) /* Clear & enable FIFOs */ +#define FCRVAL 0x0 /* Disable FIFOs */ + /* works without IRQs */ void NS16550_init (NS16550_t com_port, int baud_divisor) {