Subject: [@num@/@total@] i.MX2 family: Add basic device support From: Juergen Beisert This patch adds a few on-chip devices for i.MX21/i.MX27 procesors. TODO: - get a sign from freescale for the patch Signed-off-by: Juergen Beisert --- arch/arm/mach-mx2/devices.c | 223 ++++++++++++++++++++++++++++++ arch/arm/mach-mx2/devices.h | 27 +++ include/asm-arm/arch-mxc/imx_uart.h | 262 ++++++++++++++++++++++++++++++++++++ 3 files changed, 512 insertions(+) Index: arch/arm/mach-mx2/devices.c =================================================================== --- /dev/null +++ arch/arm/mach-mx2/devices.c @@ -0,0 +1,223 @@ +/* + * Author: MontaVista Software, Inc. + * + * + * Based on the OMAP devices.c + * + * 2005 (c) MontaVista Software, Inc. This file is licensed under the + * terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ +#include +#include +#include +#include + +#include + +/* + * Resource definition for the MXC IrDA + */ +static struct resource mxc_irda_resources[] = { + [0] = { + .start = UART3_BASE_ADDR, + .end = UART3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_UART3, + .end = INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +/* Platform Data for MXC IrDA */ +struct platform_device mxc_irda_device = { + .name = "mxc_irda", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_irda_resources), + .resource = mxc_irda_resources, +}; + +/* + * General Purpose Timer + * - i.MX1: 2 timer (slighly different register handling) + * - i.MX21: 3 timer + * - i.MX27: 6 timer + */ + +/* We use gpt0 as system timer, so do not add a device for this one */ + +static struct resource timer1_resources[] = { + [0] = { + .start = GPT2_BASE_ADDR, + .end = GPT2_BASE_ADDR + 0x17, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = INT_GPT2, + .end = INT_GPT2, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device mxc_gpt1 = { + .name = "imx_gpt", + .id = 1, + .num_resources = ARRAY_SIZE(timer1_resources), + .resource = timer1_resources +}; + +static struct resource timer2_resources[] = { + [0] = { + .start = GPT3_BASE_ADDR, + .end = GPT3_BASE_ADDR + 0x17, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = INT_GPT3, + .end = INT_GPT3, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device mxc_gpt2 = { + .name = "imx_gpt", + .id = 2, + .num_resources = ARRAY_SIZE(timer2_resources), + .resource = timer2_resources +}; + +#ifdef CONFIG_MACH_MX27 +static struct resource timer3_resources[] = { + [0] = { + .start = GPT4_BASE_ADDR, + .end = GPT4_BASE_ADDR + 0x17, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = INT_GPT4, + .end = INT_GPT4, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device mxc_gpt3 = { + .name = "imx_gpt", + .id = 3, + .num_resources = ARRAY_SIZE(timer3_resources), + .resource = timer3_resources +}; + +static struct resource timer4_resources[] = { + [0] = { + .start = GPT5_BASE_ADDR, + .end = GPT5_BASE_ADDR + 0x17, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = INT_GPT5, + .end = INT_GPT5, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device mxc_gpt4 = { + .name = "imx_gpt", + .id = 4, + .num_resources = ARRAY_SIZE(timer4_resources), + .resource = timer4_resources +}; + +static struct resource timer5_resources[] = { + [0] = { + .start = GPT6_BASE_ADDR, + .end = GPT6_BASE_ADDR + 0x17, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = INT_GPT6, + .end = INT_GPT6, + .flags = IORESOURCE_IRQ, + } +}; + +struct platform_device mxc_gpt5 = { + .name = "imx_gpt", + .id = 5, + .num_resources = ARRAY_SIZE(timer5_resources), + .resource = timer5_resources +}; +#endif + +/* + * Watchdog: + * - i.MX1 + * - i.MX21 + * - i.MX27 + */ +static struct resource mxc_wdt_resources[] = { + { + .start = WDOG_BASE_ADDR, + .end = WDOG_BASE_ADDR + 0x30, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_wdt = { + .name = "mxc_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_wdt_resources), + .resource = mxc_wdt_resources, +}; + +struct mxc_gpio_port mxc_gpio_ports[GPIO_PORT_NUM] = { + { + .num = 0, + .base = IO_ADDRESS(GPIO_BASE_ADDR), + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE, + }, { + .num = 1, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x100, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN, + }, { + .num = 2, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x200, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 2, + }, { + .num = 3, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x300, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 3, + }, { + .num = 4, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x400, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 4, + }, { + .num = 5, + .base = IO_ADDRESS(GPIO_BASE_ADDR) + 0x500, + .irq = INT_GPIO, + .virtual_irq_start = MXC_GPIO_BASE + GPIO_NUM_PIN * 5, + } +}; Index: arch/arm/mach-mx2/devices.h =================================================================== --- /dev/null +++ arch/arm/mach-mx2/devices.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2008 by Juergen Beisert + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +extern struct platform_device mxc_irda_device; +extern struct platform_device mxc_gpt0; +extern struct platform_device mxc_gpt1; +extern struct platform_device mxc_gpt2; +#ifdef CONFIG_MACH_MX27 +extern struct platform_device mxc_gpt3; +extern struct platform_device mxc_gpt4; +extern struct platform_device mxc_gpt5; +#endif +extern struct platform_device mxc_wdt; Index: include/asm-arm/arch-mxc/imx_uart.h =================================================================== --- /dev/null +++ include/asm-arm/arch-mxc/imx_uart.h @@ -0,0 +1,262 @@ +/* + * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Juergen Beisert, kernel@pengutronix.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __ASM_ARCH_MXC_UART_H__ +#define __ASM_ARCH_MXC_UART_H__ + +#ifdef __KERNEL__ + +#include +#include +#include + +/* + * The modes of the UART ports + */ +#define MODE_DTE 0 +#define MODE_DCE 1 +/* + * Is the UART configured to be a IR port + */ +#define IRDA 0 +#define NO_IRDA 1 + +/* + * This structure is used to store the the physical and virtual + * addresses of the UART DMA receive buffer. + */ +struct mxc_uart_rxdmamap { + char *rx_buf; /* DMA Receive buffer virtual address */ + dma_addr_t rx_handle; /* DMA Receive buffer physical address */ +}; + +int __init mxc_init_uart(int uart_no, unsigned int flags, + int (*init)(struct platform_device *pdev), + int (*exit)(struct platform_device *pdev)); + +#define MXC_UART_MODE_IRDA (1 << 0) +#define MXC_UART_MODE_DTE (1 << 1) +#define MXC_UART_MODE_IRDA_RX_INV (1 << 2) +#define MXC_UART_MODE_IRDA_TX_INV (1 << 3) + +/* + * This structure is a way for the low level driver to define their own + * uart_port structure. This structure includes the core uart_port + * structure that is provided by Linux as an element and has other + * elements that are specifically required by this low-level driver. + */ +struct uart_mxc_port { + /* + * The port structure holds all the information about the UART + * port like base address, and so on. + */ + struct uart_port port; + /* + * Flag to determine if the interrupts are muxed. + */ + int ints_muxed; + /* + * Array that holds the receive and master interrupt numbers + * when the interrupts are not muxed. + */ + int irqs[2]; + + int flags; + + /* + * Flag to indicate if we wish to use hardware-driven hardware + * flow control. + */ + int hardware_flow; + /* + * Holds the threshold value at which the CTS line is deasserted in + * case we use hardware-driven hardware flow control. + */ + unsigned int cts_threshold; + /* + * Flag to enable/disable DMA data transfer. + */ + int dma_enabled; + /* + * Holds the DMA receive buffer size. + */ + int dma_rxbuf_size; + /* + * DMA Receive buffers information + */ + struct mxc_uart_rxdmamap *rx_dmamap; + /* + * DMA RX buffer id + */ + int dma_rxbuf_id; + /* + * DMA Transmit buffer virtual address + */ + char *tx_buf; + /* + * DMA Transmit buffer physical address + */ + dma_addr_t tx_handle; + /* + * Holds the RxFIFO threshold value. + */ + unsigned int rx_threshold; + /* + * Holds the TxFIFO threshold value. + */ + unsigned int tx_threshold; + /* + * Information whether this is a shared UART + */ + unsigned int shared; + /* + * Clock id for UART clock + */ + struct clk *clk; + /* + * Information whether RXDMUXSEL must be set or not for IR port + */ + int rxd_mux; + /* + * DMA ID for transmit + */ + mxc_dma_device_t dma_tx_id; + /* + * DMA ID for receive + */ + mxc_dma_device_t dma_rx_id; + + int (*init)(struct platform_device *pdev); + int (*exit)(struct platform_device *pdev); +}; + +/* Address offsets of the UART registers */ +#define MXC_UARTURXD 0x000 /* Receive reg */ +#define MXC_UARTUTXD 0x040 /* Transmitter reg */ +#define MXC_UARTUCR1 0x080 /* Control reg 1 */ +#define MXC_UARTUCR2 0x084 /* Control reg 2 */ +#define MXC_UARTUCR3 0x088 /* Control reg 3 */ +#define MXC_UARTUCR4 0x08C /* Control reg 4 */ +#define MXC_UARTUFCR 0x090 /* FIFO control reg */ +#define MXC_UARTUSR1 0x094 /* Status reg 1 */ +#define MXC_UARTUSR2 0x098 /* Status reg 2 */ +#define MXC_UARTUESC 0x09C /* Escape character reg */ +#define MXC_UARTUTIM 0x0A0 /* Escape timer reg */ +#define MXC_UARTUBIR 0x0A4 /* BRM incremental reg */ +#define MXC_UARTUBMR 0x0A8 /* BRM modulator reg */ +#define MXC_UARTUBRC 0x0AC /* Baud rate count reg */ +#define MXC_UARTONEMS 0x0B0 /* One millisecond reg */ +#define MXC_UARTUTS 0x0B4 /* Test reg */ + +/* Bit definitions of UCR1 */ +#define MXC_UARTUCR1_ADEN 0x8000 +#define MXC_UARTUCR1_ADBR 0x4000 +#define MXC_UARTUCR1_TRDYEN 0x2000 +#define MXC_UARTUCR1_IDEN 0x1000 +#define MXC_UARTUCR1_RRDYEN 0x0200 +#define MXC_UARTUCR1_RXDMAEN 0x0100 +#define MXC_UARTUCR1_IREN 0x0080 +#define MXC_UARTUCR1_TXMPTYEN 0x0040 +#define MXC_UARTUCR1_RTSDEN 0x0020 +#define MXC_UARTUCR1_SNDBRK 0x0010 +#define MXC_UARTUCR1_TXDMAEN 0x0008 +#define MXC_UARTUCR1_ATDMAEN 0x0004 +#define MXC_UARTUCR1_DOZE 0x0002 +#define MXC_UARTUCR1_UARTEN 0x0001 + +/* Bit definitions of UCR2 */ +#define MXC_UARTUCR2_ESCI 0x8000 +#define MXC_UARTUCR2_IRTS 0x4000 +#define MXC_UARTUCR2_CTSC 0x2000 +#define MXC_UARTUCR2_CTS 0x1000 +#define MXC_UARTUCR2_PREN 0x0100 +#define MXC_UARTUCR2_PROE 0x0080 +#define MXC_UARTUCR2_STPB 0x0040 +#define MXC_UARTUCR2_WS 0x0020 +#define MXC_UARTUCR2_RTSEN 0x0010 +#define MXC_UARTUCR2_ATEN 0x0008 +#define MXC_UARTUCR2_TXEN 0x0004 +#define MXC_UARTUCR2_RXEN 0x0002 +#define MXC_UARTUCR2_SRST 0x0001 + +/* Bit definitions of UCR3 */ +#define MXC_UARTUCR3_DTREN 0x2000 +#define MXC_UARTUCR3_PARERREN 0x1000 +#define MXC_UARTUCR3_FRAERREN 0x0800 +#define MXC_UARTUCR3_DSR 0x0400 +#define MXC_UARTUCR3_DCD 0x0200 +#define MXC_UARTUCR3_RI 0x0100 +#define MXC_UARTUCR3_RXDSEN 0x0040 +#define MXC_UARTUCR3_AWAKEN 0x0010 +#define MXC_UARTUCR3_DTRDEN 0x0008 +#define MXC_UARTUCR3_RXDMUXSEL 0x0004 +#define MXC_UARTUCR3_INVT 0x0002 + +/* Bit definitions of UCR4 */ +#define MXC_UARTUCR4_CTSTL_OFFSET 10 +#define MXC_UARTUCR4_CTSTL_MASK (0x3F << 10) +#define MXC_UARTUCR4_INVR 0x0200 +#define MXC_UARTUCR4_ENIRI 0x0100 +#define MXC_UARTUCR4_REF16 0x0040 +#define MXC_UARTUCR4_IRSC 0x0020 +#define MXC_UARTUCR4_TCEN 0x0008 +#define MXC_UARTUCR4_OREN 0x0002 +#define MXC_UARTUCR4_DREN 0x0001 + +/* Bit definitions of UFCR */ +#define MXC_UARTUFCR_RFDIV 0x0200 /* Ref freq div is set to 2 */ +#define MXC_UARTUFCR_RFDIV_OFFSET 7 +#define MXC_UARTUFCR_RFDIV_MASK (0x7 << 7) +#define MXC_UARTUFCR_TXTL_OFFSET 10 +#define MXC_UARTUFCR_DCEDTE 0x0040 + +/* Bit definitions of URXD */ +#define MXC_UARTURXD_ERR 0x4000 +#define MXC_UARTURXD_OVRRUN 0x2000 +#define MXC_UARTURXD_FRMERR 0x1000 +#define MXC_UARTURXD_BRK 0x0800 +#define MXC_UARTURXD_PRERR 0x0400 + +/* Bit definitions of USR1 */ +#define MXC_UARTUSR1_PARITYERR 0x8000 +#define MXC_UARTUSR1_RTSS 0x4000 +#define MXC_UARTUSR1_TRDY 0x2000 +#define MXC_UARTUSR1_RTSD 0x1000 +#define MXC_UARTUSR1_FRAMERR 0x0400 +#define MXC_UARTUSR1_RRDY 0x0200 +#define MXC_UARTUSR1_AGTIM 0x0100 +#define MXC_UARTUSR1_DTRD 0x0080 +#define MXC_UARTUSR1_AWAKE 0x0010 + +/* Bit definitions of USR2 */ +#define MXC_UARTUSR2_TXFE 0x4000 +#define MXC_UARTUSR2_IDLE 0x1000 +#define MXC_UARTUSR2_RIDELT 0x0400 +#define MXC_UARTUSR2_RIIN 0x0200 +#define MXC_UARTUSR2_DCDDELT 0x0040 +#define MXC_UARTUSR2_DCDIN 0x0020 +#define MXC_UARTUSR2_TXDC 0x0008 +#define MXC_UARTUSR2_ORE 0x0002 +#define MXC_UARTUSR2_RDR 0x0001 + +/* Bit definitions of UTS */ +#define MXC_UARTUTS_LOOP 0x1000 + +#endif /* __KERNEL__ */ + +#endif /* __ASM_ARCH_MXC_UART_H__ */